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The Taiwan Semiconductor Manufacturing Company (TSMC) has increased its Chip-on-Wafer-on-Substrate (CoWoS) capacity in response to strong orders from NVIDIA Corporation, according to supply chain reports in Taiwan. TSMC, the world’s largest contract chip manufacturer, is a key NVIDIA supply chain partner for the latter’s advanced artificial intelligence chips and also one of the key bottlenecks due to capacity constraints for its packaging technology. Packaging is a key part. of the chip fabrication process, and it involves preparing the products for final use after fabrication.
NVIDIA’s production constraints are believed to be a key restraint in its ability to scale up orders to meet the massive demand for its products. This has also enabled some of its competitors to steal orders away from NVIDIA, and today’s reports suggest that TSMC has bumped up its CoWoS capacity to 15,000 wafers per month.
NVIDIA Believed to Account For 40% of TSMC’s Total CoWoS Production Capacity Say Supply Chain Sources
A surge in NVIDIA’s orders has led TSMC to increase its CoWoS capacity through a process that was started earlier this year. Reports from TSMC’s supply chain have previously pointed out that it might increase its CoWoS packaging capacity to 30,000 wafers per month by the end of this year. While this might prove to be a substantial increase, another report today shares that the capacity has been increased to 15,000 wafers after a late September report shared that TSMC had planned to boost its capacity to sit between 15,000 and 20,000 wafers by the first half of 2024.
TSMC works with several companies to source out orders for its packaging equipment, including big ticket Taiwanese semiconductor names such as ASE and the United Microelectronics Corporation (UMC). the pair had already received new orders in September.
This uptick in orders from NVIDIA has already made UMC speed up its raw material products, with the company also having entered a hot production run as of September. UMC manufactures CoWoS raw materials such as interposers, and its production capacity for these products in a facility in Singapore was 3,000 pieces as of September. The firm is reported to be interested in increasing this to 6,000 wafers per month, according to unconfirmed reports.
Today’s report also mentions the crucial role played by UMC and ASE in the packaging supply chain for NVIDIA’s artificial intelligence products. According to sources, NVIDIA is planning to diversify its packaging supply chain, and for this aim, it has contacted the two companies to also provide it with the packaging technologies. While UMC is believed to provide TSMC with raw materials such as CoWoS interposers, ASE’s production facilities are available to TSMC as a backup to release some of the pressure on its manufacturing facilities.
TSMC has bumped up its CoWoS production capacity to 15,000 wafers per month, according to the latest reports and these have come through machine modifications. This capacity is believed to double next year, by the end of which NVIDIA should account for 40% of TSMC’s CoWoS production capacity.
Market estimates have previously placed TSMC’s CoWoS production capacity at 12,000 wafers per month, so the latest report shares that there has been an improvement on this front. The firm is also believed to double its packaging capacity next year, with AMD accounting for 8% of its orders. The non-TSMC packaging supply chain can boost its production capacity by 20%.